积分梳状滤波器（CIC）的Verilog实现
总元件布局
文件名：CICDecimationFilter.v。
- DECIMATION_COEFFICIENT：抽取系数。
- STAGE_COUNT：滤波器级联级数。
- INPUT_DATA_WIDTH：输入数据位宽。
- TEMP_DATA_WIDTH：中间数据（积分器输出的数据）位宽。
- OUTPUT_DATA_WIDTH：输出位宽。
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: School of Biological Science & Medical Engineering, Southeast University
// Engineer: Picsell Dois
//
// Create Date:
// Design Name:
// Module Name: CICDecimationFilter
// Project Name:
// Target Devices:
// Tool Versions:
// Description: CIC (Cascaded Integrator Comb) Filter for signal decimation.
// Verilog code referenced from https://www.runoob.com/w3cnote/verilog-cic.html
// This CIC Filter can be customized using following options:
// DECIMATION_COEFFICIENT: Decimation coefficient of the filter. Defines the interval of data sampling.
// STAGE_COUNT: Stage (section count) of the filter. Defines the count of cascaded filters.
// INPUT_DATA_WIDTH: Width of input data.
// TEMP_DATA_WIDTH: Width of medium data output by the Integrator Module. Can be calculated with:
// TEMP_DATA_WIDTH = INPUT_DATA_WIDTH + STAGE_COUNT * ceil(log2(DECIMATION_COEFFICIENT))
// OUTPUT_DATA_WIDTH: Width of output data. OUTPUT_DATA_WIDTH must be greater or equal to INPUT_DATA_WIDTH.
//
// Dependencies: CICDecimationFilter_IntegratorModule.v
// CICDecimationFilter_DecimatorModule.v
// CICDecimationFilter_CombModule.v
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CICDecimationFilter
#(parameter DECIMATION_COEFFICIENT = 5,
parameter STAGE_COUNT = 3,
parameter INPUT_DATA_WIDTH = 12,
parameter TEMP_DATA_WIDTH = 21,
parameter OUTPUT_DATA_WIDTH = 17)
(input iClock,
input iReset,
input iIsDataValid,
input [INPUT_DATA_WIDTH-1:0] iData,
output oIsDataValid,
output [OUTPUT_DATA_WIDTH-1:0] oDecimatedData
);
wire [TEMP_DATA_WIDTH-1:0] wIntegratorOutput;
wire [TEMP_DATA_WIDTH-1:0] wDecimatorOutput;
wire wIsIntegratorOutputDataValid, wIsDecimatorOutputDataValid;
CICDecimationFilter_IntegratorModule #(.INPUT_DATA_WIDTH(INPUT_DATA_WIDTH), .OUTPUT_DATA_WIDTH(TEMP_DATA_WIDTH), .STAGE_COUNT(STAGE_COUNT))
uIntegrator(.iClock(iClock),
.iReset(iReset),
.iIsDataValid(iIsDataValid),
.iData(iData),
.oIsDataValid(wIsIntegratorOutputDataValid),
.oIntegratedData(wIntegratorOutput));
CICDecimationFilter_DecimatorModule #(.DATA_WIDTH(TEMP_DATA_WIDTH), .DECIMATION_COEFFICIENT(DECIMATION_COEFFICIENT))
uDecimator(.iClock(iClock),
.iReset(iReset),
.iIsDataValid(wIsIntegratorOutputDataValid),
.iData(wIntegratorOutput),
.oDecimatedData(wDecimatorOutput),
.oIsDataValid(wIsDecimatorOutputDataValid));
CICDecimationFilter_CombModule #(.INPUT_DATA_WIDTH(TEMP_DATA_WIDTH), .OUTPUT_DATA_WIDTH(OUTPUT_DATA_WIDTH), .STAGE_COUNT(STAGE_COUNT))
uComb(.iClock(iClock),
.iReset(iReset),
.iIsDataValid(wIsDecimatorOutputDataValid),
.iData(wDecimatorOutput),
.oIsDataValid(oIsDataValid),
.oDecimatedData(oDecimatedData));
endmodule积分器
文件名：CICDecimationFilter_IntegratorModule.v。
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: School of Biological Science & Medical Engineering, Southeast University
// Engineer: Picsell Dois
//
// Create Date:
// Design Name:
// Module Name: CICDecimationFilter_IntegratorModule
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Integrator module of a CIC Decimation Filter.
// Verilog code referenced from https://www.runoob.com/w3cnote/verilog-cic.html
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CICDecimationFilter_IntegratorModule
#(parameter INPUT_DATA_WIDTH = 12,
parameter OUTPUT_DATA_WIDTH = 21,
parameter STAGE_COUNT = 3)
(input iClock,
input iReset,
input iIsDataValid,
input [INPUT_DATA_WIDTH-1:0] iData,
output oIsDataValid,
output [OUTPUT_DATA_WIDTH-1:0] oIntegratedData
);
reg [OUTPUT_DATA_WIDTH-1:0] rIntegratedData[0:STAGE_COUNT-1];
wire [OUTPUT_DATA_WIDTH-1:0] wPaddedInputData = {{(OUTPUT_DATA_WIDTH-INPUT_DATA_WIDTH){1'b0}}, iData};
reg [STAGE_COUNT-1:0] rIsDataValid;
//Data input enable delay
always @ (posedge iClock) begin
if (iReset) begin
rIsDataValid <= 0;
end
else begin
rIsDataValid <= {rIsDataValid[STAGE_COUNT-2:0], iIsDataValid};
end
end
//Integrator stage 1
always @ (posedge iClock) begin
if (iReset) begin
rIntegratedData[0] <= 0;
end
else if (iIsDataValid) begin
rIntegratedData[0] <= rIntegratedData[0] + wPaddedInputData;
end
end
//Integrator stage 2 and higher
generate
genvar i;
for (i = 1; i < STAGE_COUNT; i = i + 1) begin : IntegratorStage
always @ (posedge iClock) begin
if (iReset) begin
rIntegratedData[i] <= 0;
end
else if (rIsDataValid[i-1]) begin
rIntegratedData[i] <= rIntegratedData[i] + rIntegratedData[i-1];
end
end
end
endgenerate
assign oIntegratedData = rIntegratedData[STAGE_COUNT-1];
assign oIsDataValid = rIsDataValid[STAGE_COUNT-1];
endmodule抽取器（降采样器）
文件名：CICDecimationFilter_DecimatorModule.v。
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: School of Biological Science & Medical Engineering, Southeast University
// Engineer: Picsell Dois
//
// Create Date:
// Design Name:
// Module Name: CICDecimationFilter_DecimatorModule
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Decimator module of a CIC Decimation Filter.
// Verilog code referenced from https://www.runoob.com/w3cnote/verilog-cic.html
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CICDecimationFilter_DecimatorModule
#(parameter DATA_WIDTH = 21,
parameter DECIMATION_COEFFICIENT = 5)
(input iClock,
input iReset,
input iIsDataValid,
input [DATA_WIDTH-1:0] iData,
output reg oIsDataValid,
output reg [DATA_WIDTH-1:0] oDecimatedData
);
reg [$clog2(DECIMATION_COEFFICIENT+1)-1:0] rCounter;
//Counter
always @(posedge iClock) begin
if (iReset) begin
rCounter <= 0;
end
else if (iIsDataValid) begin
if (rCounter == DECIMATION_COEFFICIENT-1) begin
rCounter <= 0;
end
else begin
rCounter <= rCounter + 1;
end
end
end
//Data, iIsDataValid
always @(posedge iClock) begin
if (iReset) begin
oIsDataValid <= 1'b0;
oDecimatedData <= 0;
end
else if (iIsDataValid) begin
if (rCounter == DECIMATION_COEFFICIENT-1) begin
oIsDataValid <= 1'b1;
oDecimatedData <= iData;
end
else begin
oIsDataValid <= 1'b0;
end
end
end
endmodule梳状滤波器
文件名：CICDecimationFilter_CombModule.v。
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: School of Biological Science & Medical Engineering, Southeast University
// Engineer: Picsell Dois
//
// Create Date:
// Design Name:
// Module Name: CICDecimationFilter_CombModule
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Comb module of a CIC Decimation Filter.
// Verilog code referenced from https://www.runoob.com/w3cnote/verilog-cic.html
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CICDecimationFilter_CombModule
#(parameter INPUT_DATA_WIDTH = 21,
parameter OUTPUT_DATA_WIDTH = 17,
parameter STAGE_COUNT = 3)
(input iClock,
input iReset,
input iIsDataValid,
input [INPUT_DATA_WIDTH-1:0] iData,
output reg oIsDataValid,
output reg [OUTPUT_DATA_WIDTH-1:0] oDecimatedData
);
reg [OUTPUT_DATA_WIDTH-1:0] rStageInput[0:STAGE_COUNT];
reg [OUTPUT_DATA_WIDTH-1:0] rStageOutput[0:STAGE_COUNT];
wire [OUTPUT_DATA_WIDTH-1:0] wStageOutput[0:STAGE_COUNT];
//Shift iData to keep high bits only
assign wStageOutput[0] = iData>>(INPUT_DATA_WIDTH-OUTPUT_DATA_WIDTH);
//FIR filtering for Comb module
generate
genvar i;
for (i = 1; i <= STAGE_COUNT; i = i + 1) begin : CombStage
always @ (posedge iClock) begin
if (iReset) begin
rStageInput[i] <= 0;
rStageOutput[i] <= 0;
end
else if (iIsDataValid) begin
rStageInput[i] <= wStageOutput[i-1];
rStageOutput[i] <= rStageInput[i];
end
end
assign wStageOutput[i] = rStageInput[i] - rStageOutput[i];
end
endgenerate
//Tap the output data for better display
always @(posedge iClock) begin
if (iReset) begin
oDecimatedData <= 0;
oIsDataValid <= 0;
end
else if (iIsDataValid) begin
oDecimatedData <= wStageOutput[STAGE_COUNT];
oIsDataValid <= 1'b1;
end
else begin
oIsDataValid <= 1'b0;
end
end
endmodule测试用例及测试代码
文件名：Testbench_CICDecimationFilter.v。
`timescale 1ns / 1ps
module Testbench_CICDecimationFilter;
parameter INPUT_DATA_WIDTH = 16;
parameter TEMP_DATA_WIDTH = 23;
parameter OUTPUT_DATA_WIDTH = 16;
reg rClock;
reg rReset;
reg rIsInputValid;
reg [INPUT_DATA_WIDTH-1:0] rInputData;
wire wIsOutputValid;
wire [OUTPUT_DATA_WIDTH-1:0] wOutputData;
//Clock generating
localparam CLOCK_HALF_TIME = 10;
initial begin
rClock = 1'b0;
forever begin
# CLOCK_HALF_TIME rClock = ~rClock;
end
end
//reset and finish
initial begin
rReset = 1'b1;
# 200;
rReset = 1'b0;
# (CLOCK_HALF_TIME * 2 * 2000);
$finish;
end
//Read cos data into register
parameter SIN_DATA_NUM = 200;
reg [INPUT_DATA_WIDTH-1:0] rSimData[0: SIN_DATA_NUM-1];
integer i;
initial begin
$readmemh("cosx0p25m7p5m12bit.txt", rSimData);
i = 0;
rIsInputValid = 0;
rInputData = 0;
# 300;
forever begin
@(posedge rClock) begin
rIsInputValid = 1;
rInputData = rSimData[i];
if (i == SIN_DATA_NUM-1) begin
i = 0;
end
else begin
i = i + 1;
end
end
end
end
CICDecimationFilter #(.DECIMATION_COEFFICIENT(5), .STAGE_COUNT(3), .INPUT_DATA_WIDTH(INPUT_DATA_WIDTH), .TEMP_DATA_WIDTH(TEMP_DATA_WIDTH), .OUTPUT_DATA_WIDTH(OUTPUT_DATA_WIDTH))
uCIC(.iClock(rClock),
.iReset(rReset),
.iIsDataValid(rIsInputValid),
.iData(rInputData),
.oIsDataValid(wIsOutputValid),
.oDecimatedData(wOutputData));
endmodule测试用例：cosx0p25m7p5m12bit.txt
fff
e53
ab0
814
8a4
be6
f26
fb3
d12
968
7b3
954
cea
f77
ed6
b81
82c
789
a11
da0
f39
d7a
9c4
716
793
ac3
df2
e6d
bbb
800
63b
7cc
b52
dcf
d20
9bd
659
5a8
823
ba6
d33
b68
7a8
4ef
562
888
bae
c21
967
5a6
3da
565
8e5
b5e
aab
744
3de
32b
5a4
926
ab2
8e8
529
271
2e7
610
939
9b0
6fb
33f
179
30a
692
912
867
509
1ad
103
388
714
8ac
6ee
33b
91
114
44b
783
809
563
1b6
1
1a2
53b
7cc
733
3e7
9c
5
29c
63c
7e6
63c
29c
5
9c
3e7
733
7cc
53b
1a2
1
1b6
563
809
783
44b
114
91
33b
6ee
8ac
714
388
103
1ad
509
867
912
692
30a
179
33f
6fb
9b0
939
610
2e7
271
529
8e8
ab2
926
5a4
32b
3de
744
aab
b5e
8e5
565
3da
5a6
967
c21
bae
888
562
4ef
7a8
b68
d33
ba6
823
5a8
659
9bd
d20
dcf
b52
7cc
63b
800
bbb
e6d
df2
ac3
793
716
9c4
d7a
f39
da0
a11
789
82c
b81
ed6
f77
cea
954
7b3
968
d12
fb3
f26
be6
8a4
814
ab0
e53参考资料
页面版本: 5, 最后编辑于: 23 May 2023 13:11